Marcin Kowalczyk, MSc Research & Teaching Assistant PhD Student kowalczyk@agh.edu.pl
My interests are focused on real-time vision systems for autonomous robots. In my research, I use heterogeneous computing platforms and high-level environments enabling the modelling of algorithms and designed systems. My research also concerns the use of neuromorphic event sensors in modern vision data processing systems that require the development of new data processing methods.
Academic service 3
Chair
2026
DASIP 2026 – Workshop on Design and Architectures for Signal and Image Processing, Kraków
Steering Committee member
2027
DASIP – Workshop on Design and Architectures for Signal and Image Processing
TPC member
2026
DSD – Euromicro Conference on Digital System Design
Publications
Year
Type
Project
Joint papers with
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@inproceedings{badap-agh:167206,title={Towards event-based in-cabin sensing: a synchronized dual-camera dataset pipeline},author={Kowalczyk, Marcin and Dlugosz, Marek and Jeziorek, Kamil and Komorkiewicz, Mateusz and Kryjak, Tomasz and Marchewka, Dariusz and Szelest, Marcin and Wzorek, Piotr and Skruch, Pawel},year={2026},series={KU KDM~2026 : eighteenth ACC Cyfronet AGH HPC users conference : Zakopane, 13–15 April~2026 : proceedings},pages={41–42},collection={KU KDM~2026 : eighteenth ACC Cyfronet AGH HPC users conference : Zakopane, 13–15 April~2026 : proceedings},projects={ARTIQ, Preludium-Kowalczyk},}
This paper presents a hardware architecture that implements the Contrast Maximization (CM) algorithm in Field-Programmable Gate Array (FPGA) resources for event-based vision systems. CM estimates motion parameters by maximizing the contrast of an Image of Warped Events (IWE) reconstructed from asynchronous event streams. Event-based vision sensors generate sparse data with high temporal resolution and low spatial redundancy, which makes them well suited for hardware processing. The deterministic, massively parallel structure of the FPGA is leveraged to design a deeply pipelined architecture capable of high-throughput, energy-efficient processing suitable for real-time embedded applications. This paper details the hardware modules responsible for event warping, contrast computation, and iterative optimization, discusses key implementation decisions, and presents the hardware-aware optimization method used in the design. Experimental results demonstrate a substantial speed and efficiency improvement over CPU- and GPU-based implementations, with motion parameter estimation executing over 200 times faster. To the best of our knowledge, this is the first hardware architecture enabling acceleration of CM algorithm computations. Its performance is evaluated in terms of processing speed, energy efficiency, and hardware resource utilization. The proposed design is validated using an event-based object tracking application. The results confirm that the architecture provides a solid foundation for real-time motion estimation in high-speed, low-power embedded systems.
@inproceedings{badap-agh:169140,title={FPGA-based hardware architecture for contrast maximization in event-based vision},author={Filipkowski, Michal and Kowalczyk, Marcin and Kryjak, Tomasz},year={2026},projects={Preludium-Kowalczyk},series={Applied Reconfigurable Computing : architectures, tools, and applications : 22nd international symposium, ARC~2026 : Cagliari, Sardinia, Italy, April 8–10,~2026 : proceedings},pages={309–325},doi={10.1007/978-3-032-29365-7_19},collection={Applied Reconfigurable Computing : architectures, tools, and applications : 22nd international symposium, ARC~2026 : Cagliari, Sardinia, Italy, April 8–10,~2026 : proceedings},}
In recent years, there has been rapid development in the field of event vision. It manifests itself both on the technical side, as better and better event sensors are available, and on the algorithmic side, as more and more applications of this technology are proposed and scientific papers are published. However, the data stream from these sensors typically contains a significant amount of noise, which varies depending on factors such as the degree of illumination in the observed scene or the temperature of the sensor. We propose a hardware architecture of the Distance-based Interpolation with Frequency Weights(DIF) filter and implement it on an FPGA chip. To evaluate the algorithm and compare it with other solutions, we have prepared a new high-resolution event dataset, which we are also releasing to the community. Our architecture achieved a throughput of 403.39 million events per second (MEPS) for a sensor resolution of 1280 × 720 and 428.45 MEPS for a resolution of 640 × 480. The averagevalues of the Area Under the Receiver Operating Characteristic (AUROC) index ranged from 0.844 to 0.999, depending on the dataset, which is comparable to the state-of-the-art filtering solutions, but with much higher throughput and better operation over a wide range of noise levels.
@article{badap-agh:160777,title={High throughput event filtering: the interpolation-based DIF algorithm hardware architecture},author={Kowalczyk, Marcin and Kryjak, Tomasz},year={2025},projects={Preludium-Kowalczyk},journal={Microprocessors and Microsystems},series={Microprocessors and Microsystems},volume={117},pages={105171},doi={10.1016/j.micpro.2025.105171},issn={0141-9331},collection={Microprocessors and Microsystems},}
Event-based sensors offer significant advantages over traditional frame-based cameras, especially in scenarios involving rapid motion or challenging lighting conditions. However, event data frequently suffers from considerable noise, negatively impacting the performance and robustness of deep learning models. Traditionally, this problem has been addressed by applying filtering algorithms to the event stream, but this may also remove some of relevant data. In this paper, we propose a novel noise-injection training methodology designed to enhance the neural networks robustness against varying levels of event noise. Our approach introduces controlled noise directly into the training data, enabling models to learn noise-resilient representations. We have conducted extensive evaluations of the proposed method using multiple benchmark datasets (N-Caltech101, N-Cars, and Mini N-ImageNet) and various network architectures, including Convolutional Neural Networks, Vision Transformers, Spiking Neural Networks, and Graph Convolutional Networks. Experimental results show that our noise-injection training strategy achieves stable performance over a range of noise intensities, consistently outperforms event-filtering techniques, and achieves the highest average classification accuracy, making it a viable alternative to traditional event-data filtering methods in an object classification system. Code: https://github.com/vision-agh/DVS_Filtering
@inproceedings{badap-agh:162623,title={Learning from noise: enhancing DNNs for event-based vision through controlled noise injection},author={Kowalczyk, Marcin and Jeziorek, Kamil and Kryjak, Tomasz},year={2025},projects={Preludium-Kowalczyk},series={CVPRW~2025 [Dokument elektroniczny] : IEEE/CVF Computer Vision and Pattern Recognition Workshops : 11–15 June~2025, Nashville, [USA] : proceedings},pages={5092–5102},doi={10.1109/CVPRW67362.2025.00504},collection={CVPRW~2025 [Dokument elektroniczny] : IEEE/CVF Computer Vision and Pattern Recognition Workshops : 11–15 June~2025, Nashville, [USA] : proceedings},}
For perception systems in mobile robotics - particularly in demanding, highly dynamic environments - event cameras (DVS - Dynamic Vision Sensors) are being increasingly utilised as an alternative to conventional vision sensors. The real-time processing of the registered spatio-temporal sparse point cloud must satisfy stringent requirements in terms of latency, throughput, and energy efficiency. In this demonstration, we present our method for implementing Graph Convolutional Neural Networks on a heterogeneous SoC FPGA platform, aimed at meeting these constraints. We address the challenges associated with integrating event-based sensors with reconfigurable hardware, as well as the intricate relationship between latency, performance, and hardware resource utilisation.
@inproceedings{badap-agh:166922,title={Live demonstration: Continuous processing of event-data with Graph Convolutional Neural Networks implemented for SoC FPGA},author={Wzorek, Piotr and Jeziorek, Kamil and Kowalczyk, Marcin and Blachut, Krzysztof and Kryjak, Tomasz and Gorgon, Marek},year={2025},series={FPL~2025 [Dokument elektroniczny] : 35th International Conference on Field-Programmable Logic and Applications : 1–5 September~2025 Leiden, Netherlands : proceedings},pages={359},doi={10.1109/FPL68686.2025.00065},collection={FPL~2025 [Dokument elektroniczny] : 35th International Conference on Field-Programmable Logic and Applications : 1–5 September~2025 Leiden, Netherlands : proceedings},projects={Preludium-Wzorek, Preludium-Kowalczyk},}
The field of neuromorphic vision is developing rapidly, and event cameras are finding their way into more and more applications. However, the data stream from these sensors is characterised by significant noise. In this paper, we propose a method for event data that is capable of removing approximately 99% of noise while preserving the majority of the valid signal. We have proposed four algorithms based on the matrix of infinite impulse response (IIR) filters method. We compared them on several event datasets that were further modified by adding artificially generated noise and noise recorded with dynamic vision sensor. The proposed methods use about 30KB of memory for a sensor with a resolution of 1280 × 720 and is therefore well suited for implementation in embedded devices.
@inproceedings{badap-agh:148668,title={Interpolation-based event visual data filtering algorithms},author={Kowalczyk, Marcin and Kryjak, Tomasz},year={2023},projects={Preludium-Kowalczyk},series={CVPRW~2023 [Dokument elektroniczny] : 2023 IEEE/CVF conference on Computer Vision and Pattern Recognition Workshops : Vancouver, Canada 18-22 June 2023 : proceedings},pages={4056–4064},doi={10.1109/CVPRW59228.2023.00425},collection={CVPRW~2023 [Dokument elektroniczny] : 2023 IEEE/CVF conference on Computer Vision and Pattern Recognition Workshops : Vancouver, Canada 18-22 June 2023 : proceedings},}
This paper proposes the use of an event camera as a component of a vision system that enables counting of fast-moving objects – in this case, falling corn grains. These cameras transmit, in an asynchronous manner, information about the change in brightness of individual pixels and are characterised by low latency, no motion blur, and correct operation in different lighting conditions, as well as very low power consumption. The proposed counting algorithm processes events in real time. The operation of the solution was demonstrated on a stand consisting of a chute with a vibrating feeder, which allowed the number of falling grains to be adjusted. The objective of the control system with a PID controller was to maintain a constant average number of falling objects. The proposed solution was subjected to a series of tests to determine the correctness of the developed method operation. On their basis, the validity of using an event camera to count small, fast-moving objects and the associated wide range of potential industrial applications can be confirmed.
@article{badap-agh:145827,title={Zliczanie szybkich obiekt\'{o}w z wykorzystaniem kamery zdarzeniowej},author={Bialik, Kamil and Kowalczyk, Marcin and Blachut, Krzysztof and Kryjak, Tomasz},year={2023},projects={Preludium-Kowalczyk},journal={PAR Pomiary Automatyka Robotyka},series={PAR Pomiary Automatyka Robotyka},volume={27},number={1},pages={79},doi={10.14313/PAR_247/79},issn={1427-9126},collection={PAR Pomiary Automatyka Robotyka},}
In Progress in image processing, pattern recognition and communication systems : proceedings of the conference (CORES, IP&C, ACS) – June 28–30 2021, 2022
Deep learning algorithms are a key component of many state-of-the-art vision systems, especially as Convolutional Neural Networks (CNN) outperform most solutions in the sense of accuracy. To apply such algorithms in real-time applications, one has to address the challenges of memory and computational complexity. To deal with the first issue, we use networks with reduced precision, specifically a binary neural network (also known as XNOR). To satisfy the computational requirements, we propose to use highly parallel and low-power FPGA devices. In this work, we explore the possibility of accelerating XNOR networks for traffic sign classification. The trained binary networks are implemented on the ZCU 104 development board, equipped with a Zynq UltraScale+ MPSoC device using two different approaches. Firstly, we propose a custom HDL accelerator for XNOR networks, which enables the inference with almost 450 fps. Even better results are obtained with the second method - the Xilinx FINN accelerator - enabling to process input images with around 550 frame rate. Both approaches provide over 96% accuracy on the test set.
@inproceedings{badap-agh:136486,title={Exploration of hardware acceleration methods for an XNOR traffic signs classifier},author={Przewlocka-Rus, Dominika and Kowalczyk, Marcin and Kryjak, Tomasz},year={2022},projects={Preludium-Kowalczyk},series={Progress in image processing, pattern recognition and communication systems : proceedings of the conference (CORES, IP\&C, ACS) – June 28–30 2021},pages={34–45},doi={10.1007/978-3-030-81523-3_4},collection={Progress in image processing, pattern recognition and communication systems : proceedings of the conference (CORES, IP\&C, ACS) – June 28–30 2021},}
Neuromorphic vision is a rapidly growing field with numerous applications in the perception systems of autonomous vehicles. Unfortunately, due to the sensors working principle, there is a significant amount of noise in the event stream. In this paper we present a novel algorithm based on an IIR filter matrix for filtering this type of noise and a hardware architecture that allows its acceleration using an SoC FPGA. Our method has a very good filtering efficiency for uncorrelated noise - over 99% of noisy events are removed. It has been tested for several event data sets with added random noise. We designed the hardware architecture in such a way as to reduce the utilisation of the FPGA’s internal BRAM resources. This enabled a very low latency and a throughput of up to 385.8 MEPS million events per second. The proposed hardware architecture was verified in simulation and in hardware on the Xilinx Zynq Ultrascale+ MPSoC chip on the Mercury+ XU9 module with the Mercury+ ST1 base board.
@inproceedings{badap-agh:145044,title={Hardware architecture for high throughput event visual data filtering with matrix of IIR filters algorithm},author={Kowalczyk, Marcin and Kryjak, Tomasz},year={2022},projects={Preludium-Kowalczyk},series={DSD~2022 [Dokument elektroniczny] : 25th~Euromicro Conference on Digital System Design : 31 August – 2 September 2022, Maspalomas, Spain : proceedings},pages={284–291},doi={10.1109/DSD57027.2022.00046},collection={DSD~2022 [Dokument elektroniczny] : 25th~Euromicro Conference on Digital System Design : 31 August – 2 September 2022, Maspalomas, Spain : proceedings},}
Streszczenie: Systemy wizyjne to dynamicznie rozwijająca się dziedzina nauki i techniki.W niniejszym artykule przedstawiono przegląd zagadnień, nad którymi pracuje zespół Laboratorium Systemów Wizyjnych.Obejmuje on systemy wizyjne dla pojazdów autonomicznych, aplikacje analizy obrazów medycznych, systemy wspomagania szkolenia pracowników, analizę obrazów termowizyjnych, implementacje i akceleracje algorytmów wizyjnych w układach SoC FPGA i GPU, przetwarzanie strumienia wizyjnego w rozdzielczości 4K, a także analizę sygnałów z wykorzystaniem głębokich sieci neuronowych i współpracę przy eksperymencie ALICE w CERN-ie.
@inbook{badap-agh:141409,title={Systemy wizyjne w zastosowaniach przemyslowych},author={Gorgon, Marek and Aleksandrowicz, Maciej and Blachut, Krzysztof and Brodzicki, Andrzej and Bublinski, Zbigniew and Cyba, Artur and Danilowicz, Michal and Glowacz, Adam and Jablonski, Miroslaw and Jaworek-Korjakowska, Joanna and Kostuch, Aleksander and Kowalczyk, Marcin and Kryjak, Tomasz and Kucharski, Dariusz and Lis, Konrad and Machura, Michal and Mikrut, Zbigniew and Pawlik, Piotr and Piekarski, Michal and Przewlocka-Rus, Dominika and Lis, Joanna and Szolc, Hubert and Wasala, Mateusz and Wojcicka, Anna Malgorzata and Wzorek, Piotr},year={2022},projects={Preludium-Kowalczyk},series={Nauka – technika – technologia : seria wydawnicza AGH},volume={T.~5},pages={17–31},doi={10.7494/978-83-67427-00-5_1},collection={Nauka – technika – technologia : seria wydawnicza AGH},}
In FPL 2021 : 31st international conference on Field-Programmable Logic and Applications : Dresden, Germany 30 August – 3 September 2021 : proceedings, 2021
This work presents a comparison of hardware architectures realising a connected component labelling (CCL) algorithm in reprogrammable logic. The architectures are capable of processing a video stream with 4K/UltraHD resolution at 60 frames per second in real-time. The modules were verified in simulation and in hardware on the Xilinx Zynq Ultrascale+ MPSoC chip on the ZCU104 evaluation board.
@inproceedings{badap-agh:137405,title={A comparison of real-time 4K/UltraHD connected component labelling architectures},projects={Sonata, Preludium-Kowalczyk},author={Kowalczyk, Marcin and Kryjak, Tomasz},year={2021},series={FPL~2021 [Dokument elektroniczny] : 31st international conference on Field-Programmable Logic and Applications : Dresden, Germany 30 August – 3 September 2021 : proceedings},pages={401–401},doi={10.1109/FPL53798.2021.00086},collection={FPL~2021 [Dokument elektroniczny] : 31st international conference on Field-Programmable Logic and Applications : Dresden, Germany 30 August – 3 September 2021 : proceedings},}
This work describes the hardware implementation of a connected component labelling (CCL) module in reprogammable logic. The main novelty of the design is the "full", i.e. without any simplifications, support of a 4 pixel per clock format (4 ppc) and real-time processing of a 4K/UltraHD video stream (3840 x 2160 pixels) at 60 frames per second. To achieve this, a special labelling method was designed and a functionality that stops the input data stream in order to process pixel groups which require writing more than one merger into the equivalence table. The proposed module was verified in simulation and in hardware on the Xilinx Zynq Ultrascale+ MPSoC chip on the ZCU104 evaluation board.
@inproceedings{badap-agh:137005,title={A connected component labelling algorithm for a multi-pixel per clock cycle video stream},author={Kowalczyk, Marcin and Kryjak, Tomasz},year={2021},projects={Preludium-Kowalczyk},series={2021~24th~Euromicro conference on Digital System Design [Dokument elektroniczny] : DSD~2021 : virtual conference, 1–3 September 2021 : proceedings},pages={43–50},doi={10.1109/DSD53832.2021.00016},collection={2021~24th~Euromicro conference on Digital System Design [Dokument elektroniczny] : DSD~2021 : virtual conference, 1–3 September 2021 : proceedings},}
In this paper, a hardware implementation in reconfigurable logic of a single-pass connected component labelling (CCL) and connected component analysis (CCA) module is presented. The main novelty of the design is the support of a video stream in 2 and 4 pixel per clock format (2 and 4 ppc) and real-time processing of 4K/UHD video stream (3840 x 2160 pixels) at 60 frames per second. We discuss several approaches to the issue and present in detail the selected ones. The proposed module was verified in an exemplary application – skin colour areas segmentation – on the ZCU 102 and ZCU 104 evaluation boards equipped with Xilinx Zynq UltraScale+ MPSoC devices.
@article{badap-agh:134265,title={Real-time FPGA implementation of parallel connected component labelling for a 4K video stream},projects={Sonata, Preludium-Kowalczyk},author={Kowalczyk, Marcin and Ciarach, Piotr and Przewlocka-Rus, Dominika and Szolc, Hubert and Kryjak, Tomasz},year={2021},journal={Journal of Signal Processing Systems for Signal, Image, and Video Technology},series={Journal of Signal Processing Systems for Signal, Image, and Video Technology},volume={93},number={5},pages={481},doi={10.1007/s11265-021-01636-4},issn={1939-8018},collection={Journal of Signal Processing Systems for Signal, Image, and Video Technology},}
In this paper, a hardware implementation in reconfigurable logic of a single-pass connected component labelling (CCL) and connected component analysis (CCA) module is presented. The main novelty of the design is the support of a video stream in 2 and 4 pixel per clock format (2 and 4 ppc) and real-time processing of 4K/UHD video stream (3840 x 2160 pixels) at 60 frames per second. We discuss several approaches to the issue and present in detail the selected ones. The proposed module was verified in an exemplary application – skin colour areas segmentation – on the ZCU 102 and ZCU 104 evaluation boards equipped with Xilinx Zynq UltraScale+ MPSoC devices.
@inproceedings{badap-agh:121175,title={Real-time FPGA implementation of connected component labelling for a 4K video stream},projects={Sonata},author={Ciarach, Piotr and Kowalczyk, Marcin and Przewlocka-Rus, Dominika and Kryjak, Tomasz},year={2019},series={Applied Reconfigurable Computing : 15th~international symposium, ARC~2019 : Darmstadt, Germany, April 9–11, 2019 : proceedings},pages={165–180},doi={10.1007/978-3-030-17227-5_13},collection={Applied Reconfigurable Computing : 15th~international symposium, ARC~2019 : Darmstadt, Germany, April 9–11, 2019 : proceedings},}
In this paper a hardware-software implementation of adaptive correlation filter tracking for a 3840 × 2160 @ 60 fps video stream in a Zynq UltraScale+ MPSoC is discussed. Correlation filters gained popularity in recent years because of their efficiency and good results in the VOT (Visual Object Tracking) challenge. An implementation of the MOSSE (Minimum Output Sum of Squared Error) algorithm is presented. It utilizes 2-dimensional FFT for computing correlation and updates filter coefficients in every frame. The initial filter coefficients are computed on the ARM processor in the PS (Processing System), while all other operations are preformed in PL (Programmable Logic). The presented architecture was described with the use of Verilog hardware description language.
@inproceedings{badap-agh:126251,title={Real-time implementation of adaptive correlation filter tracking for 4K video stream in Zynq UltraScale+ MPSoC},projects={Sonata},author={Kowalczyk, Marcin and Przewlocka-Rus, Dominika and Kryjak, Tomasz},year={2019},series={dasip [Dokument elektroniczny] : conference on Design and Architectures for Signal and Image Processing : 16–18 October, 2019, Montr\'{e}al, Canada},pages={53–58},doi={10.1109/DASIP48288.2019.9049203},collection={dasip [Dokument elektroniczny] : conference on Design and Architectures for Signal and Image Processing : 16–18 October, 2019, Montr\'{e}al, Canada},}
In dasip : the conference on Design and Architectures for Signal and Image Processing : TEXPO graduate student research competition : 16–18 October, 2019, Montréal, Canada, 2019
@inproceedings{badap-agh:126253,title={XNOR CNNs in FPGA: real-time detection and classification of traffic signs in 4K – a demo},projects={Sonata},author={Przewlocka-Rus, Dominika and Kowalczyk, Marcin and Kryjak, Tomasz},year={2019},series={dasip [Dokument elektroniczny] : the conference on Design and Architectures for Signal and Image Processing : TEXPO graduate student research competition : 16–18 October, 2019, Montr\'{e}al, Canada},pages={1–1},url={https://dasip-conference.org/wp-content/uploads/sites/2/2019/10/DASIP2019_paper_34.pdf},collection={dasip [Dokument elektroniczny] : the conference on Design and Architectures for Signal and Image Processing : TEXPO graduate student research competition : 16–18 October, 2019, Montr\'{e}al, Canada},}
In this paper hardware implementation of selected contextual based image pre-processing modules for a 3840×2160 @60 FPS video stream in a Zynq UltraScale+ MPSoC is discussed. The following operations are considered: simple averaging (box filter), Gaussian filter, edge detection using the Sobel and Canny methods, median filter and morphological erosion and dilation operations. The scheme for implementing contextual based operations for a video stream in the format of 2 and 4 pixels per clock and challenges related to the pipelined implementation of processing such data are described. Also the use of logic resources and energy efficiency of modules described in the Verilog hardware description language and using the High Level Synthesis tools (Vivado HLS, SDSoC and xfOpenCV library) are compared. All designed modules support real-time processing of a 4K@60 FPS video stream.
@inproceedings{badap-agh:119438,title={Real-time implementation of contextual image processing operations for 4K video stream in Zynq UltraScale+ MPSoC},projects={Sonata},author={Kowalczyk, Marcin and Przewlocka-Rus, Dominika and Kryjak, Tomasz},year={2018},series={dasip [Dokument elektroniczny] : the 2018~conference on Design \& Architectures for Signal \& Image Processing : Porto, Portugal, October 10–12, 2018},pages={37–42},doi={10.1109/DASIP.2018.8597105},collection={dasip [Dokument elektroniczny] : the 2018~conference on Design \& Architectures for Signal \& Image Processing : Porto, Portugal, October 10–12, 2018},}
@inproceedings{badap-agh:118432,title={Real-time implementation of contextual image processing operations for 4K video stream in Zynq UltraScale+ MPSoC – a~demo},projects={Sonata},author={Kowalczyk, Marcin and Przewlocka-Rus, Dominika and Kryjak, Tomasz},year={2018},series={dasip~2018 [Dokument elektroniczny] : conference on Design and Architectures for Signal and Image Processing : October 10–12 2018, Porto, Portugal},pages={1–2},url={https://web.fe.up.pt/~specs/events/dasip2018/files/paper_46.pdf},collection={dasip~2018 [Dokument elektroniczny] : conference on Design and Architectures for Signal and Image Processing : October 10–12 2018, Porto, Portugal},}
2017
ZSTN
Object tracking using a moving camera based on object detection and connected component labelling implemented in Zynq SoC
@article{badap-agh:109620,title={Object tracking using a moving camera based on object detection and connected component labelling implemented in Zynq SoC},author={Kowalczyk, Marcin and Ciarach, Piotr and Kryjak, Tomasz},year={2017},journal={Zeszyty Studenckiego Towarzystwa Naukowego},series={Zeszyty Studenckiego Towarzystwa Naukowego},pages={141},issn={1732-0925},collection={Zeszyty Studenckiego Towarzystwa Naukowego},}
DASIP
Object tracking with the use of a moving camera implemented in heterogeneous Zynq SoC – a demo
In this paper a hardware-software design of an object tracking system, which uses a moving camera is presented. The solution is implemented on the Zybo development board with the Zynq SoC (System on Chip) device from Xilinx. The object’s position is used to control two servomotors, which constitute a pan-tilt mounting of the camera. The proposed system is able to process a 1280 x 720 @ 60 fps video stream in real-time and track moving objects.
@inproceedings{badap-agh:109750,title={Object tracking with the use of a moving camera implemented in heterogeneous Zynq SoC – a~demo},author={Kowalczyk, Marcin and Kryjak, Tomasz and Gorgon, Marek},year={2017},series={dasip~2017 [Dokument elektroniczny] : conference on Design and Architectures for Signal and Image Processing : September 27–29, 2017, Dresden},pages={1–2},url={https://ieeexplore.ieee.org/document/8122123},collection={dasip~2017 [Dokument elektroniczny] : conference on Design and Architectures for Signal and Image Processing : September 27–29, 2017, Dresden},}
KKA
Object tracking with the use of a moving camera implemented in heterogeneous Zynq System on Chip
In Trends in Advanced Intelligent Control, Optimization and Automation : proceedings of KKA 2017 – the 19th Polish Control Conference, Kraków, Poland, June 18–21, 2017, 2017
In this paper a hardware-software design of an object tracking system, which uses a moving camera is presented. The solution is implemented on the Zybo development board with the Zynq SoC (System on Chip) device from Xilinx. The object’s position is used to control two servomotors, which constitute a pan-tilt mounting of the camera. The proposed system is able to process a 1280 × 720 @ 60 fps video stream in real-time and track moving objects.
@inproceedings{badap-agh:106487,title={Object tracking with the use of a moving camera implemented in heterogeneous Zynq System on Chip},author={Kowalczyk, Marcin and Kryjak, Tomasz},year={2017},series={Trends in Advanced Intelligent Control, Optimization and Automation : proceedings of KKA 2017 -- the 19th Polish Control Conference, Krak\'{o}w, Poland, June 18–21, 2017},pages={354–363},doi={10.1007/978-3-319-60699-6_34},collection={Trends in Advanced Intelligent Control, Optimization and Automation : proceedings of KKA 2017 -- the 19th Polish Control Conference, Krak\'{o}w, Poland, June 18–21, 2017},}
2015
DASIP
FPGA based system for real-time structure from motion computation
In this paper a system for real-time structure from motion computation is presented. The module is dedicated for a video based Advanced Driver Assistance System, where information about the surrounding environment and scene depth is often required to facilitate advanced applications. A heterogeneous System on a Chip solution, based on a FPGA device and an ARM processor is presented. The described hardware-software co-design is able to perform all steps required for structure from motion computation: feature extraction for every video frame, feature matching between two consecutive frames, finding the fundamental matrix, recovering the projection matrix and points triangulation. The design space exploration for the hardware part of the system is presented, which clearly points out the tradeoffs between resource usage, maximum clock and results accuracy. The system can process in real-time the images of 720x576 pixel resolution @ 50 fps. While the triangulation module allows for even high definition images processing and is able to compute results for up to 388 million points per second.
@inproceedings{badap-agh:93233,title={FPGA based system for real-time structure from motion computation},author={Komorkiewicz, Mateusz and Kryjak, Tomasz and Chuchacz-Kowalczyk, Katarzyna and Skruch, Pawel and Gorgon, Marek},year={2015},series={dasip [Dokument elektroniczny] : proceedings of the 2015~conference on Design \& Architectures for Signal \& Image Processing : Cracow, Poland, September 23–25, 2015},pages={28–34},collection={dasip [Dokument elektroniczny] : proceedings of the 2015~conference on Design \& Architectures for Signal \& Image Processing : Cracow, Poland, September 23–25, 2015},}
