Krzysztof Błachut, MSc | Embedded Perception and Autonomous Systems Group

Krzysztof Błachut, MSc
Research & Teaching Assistant
PhD Student
kblachut@agh.edu.pl

My research interests include embedded vision systems in flying and driving autonomous vehicles and in video surveillance systems. I use heterogeneous computing platforms with a particular focus on FPGAs for real-time implementation of frame and event-based data processing algorithms.

Computer Vision Event Cameras Graph Neural Networks Hardware Acceleration Object Detection Optical Flow Real-Time Processing SoC FPGA

Experience 2

Research & Teaching Assistant
October 2022 – Present

AGH University of Krakow

Research in hardware-accelerated image and video processing domains. Teaching students about implementation of vision algorithms on reprogrammable FPGA devices and in Python.
Software tester
July 2017 – September 2017

Visiona Sp. z o.o.

Testing of web applications.

Education 3

PhD candidate
2019 – Present

AGH Doctoral School, AGH University of Krakow

Automation, Electronics, Electrical Engineering and Space Technologies
Master of Science
2018 – 2019

AGH University of Krakow

Automatic Control and Robotics – Intelligent Control Systems – Vision Systems
Bachelor of Engineering
2014 – 2018

AGH University of Krakow

Automatic Control and Robotics

Awards 1

AMD Open Hardware Design Competition 2024 – Winner (PhD category)
28 August 2024

AMD

Graph Convolutional Neural Networks for Event-Based Vision for AMD SoC FPGA

Publications

2026

TRETS
Hardware-accelerated graph neural networks: an alternative approach for event-based audio classification and keyword spotting on SoC FPGA

Kamil Jeziorek, Piotr Wzorek, Krzysztof Blachut, Hiroshi Nakano, Manon Dampfhoffer, and 4 more authors

ACM Transactions on Reconfigurable Technology and Systems, 2026

Abstract DOI Bib

As the volume of data recorded by embedded edge sensors increases, particularly from neuromorphic devices producing discrete event streams, there is a need for hardware-aware neural architectures that enable efficient, low-latency and energy-conscious local processing. To address this research gap, we present an FPGA implementation of event-graph neural networks for audio processing. We utilise an artificial cochlea that converts time-series signals into sparse event data, reducing memory and computation costs. Our architecture was implemented on an SoC FPGA and evaluated on two open source datasets. For the classification task, our baseline floating-point model achieves 92.7% accuracy on the SHD dataset—only 2.4% and 2% below the state-of-the-art—while requiring 10 and 67 fewer parameters, respectively. Compared to FPGA-based spiking neural networks, our quantised model reaches 92.3% accuracy, outperforming them by 19.3 pps while reducing resource usage and latency. For the SSC dataset, we report the first hardware-accelerated evaluation, and our models achieve 66.9–71.0% accuracy. Extending our conference work, we further demonstrate the first end-to-end FPGA implementation of the event-audio keyword spotting task, combining graph convolutional layers with recurrent sequence modelling for continuous, streaming operation. The system achieves 95% word-end detection accuracy, with only 10.53 µs latency and 1.18 W power consumption, establishing a strong benchmark for energy-efficient event-driven KWS.
@article{badap-agh:170304, title = {Hardware-accelerated graph neural networks: an alternative approach for event-based audio classification and keyword spotting on SoC FPGA}, author = {Jeziorek, Kamil and Wzorek, Piotr and Blachut, Krzysztof and Nakano, Hiroshi and Dampfhoffer, Manon and Mesquida, Thomas and Nishi, Hiroaki and Dalgaty, Thomas and Kryjak, Tomasz}, year = {2026}, journal = {ACM Transactions on Reconfigurable Technology and Systems}, volume = {19}, pages = {45}, doi = {10.1145/3838800}, }
JSA Preludium
Embedded graph convolutional networks for real-time event data processing on SoC FPGAs

Kamil Jeziorek, Piotr Wzorek, Krzysztof Blachut, Andrea Pinna, and Tomasz Kryjak

Journal of Systems Architecture, 2026

Abstract Collaboration DOI arXiv Bib
- SYEL (Systèmes Électroniques), LIP6 laboratory
  Sorbonne Université, France
All our collaborations
The utilisation of event cameras represents an important and swiftly evolving trend aimed at addressing the constraints of traditional video systems. Particularly within the automotive domain, these cameras find significant relevance for their integration into embedded real-time systems due to lower latency and power consumption. One effective approach to ensure the necessary throughput and latency for event processing is through the utilisation of graph convolutional networks (GCNs). In this study, we introduce a custom EFGCN (Event-based FPGA-accelerated Graph Convolutional Network) designed with a series of hardware-aware optimisations tailored for PointNetConv, a graph convolution designed for point cloud processing. The proposed techniques result in up to 100-fold reduction in model size compared to Asynchronous Event-based GNN (AEGNN), one of the most recent works in the field, with a relatively small decrease in accuracy (2.9% for the N-Caltech101 classification task, 2.2% for the N-Cars classification task), thus following the TinyML trend. We implemented EFGCN on a ZCU104 SoC FPGA platform without any off-chip external memory resources, achieving a throughput of 13.3 million events per second (MEPS) and real-time partially asynchronous processing with low latency. Across multiple event-based classification benchmarks, our approach achieves competitive accuracy while providing state-of-the-art computational efficiency per event, small model size, and high scalability, customisability and resource efficiency. We publish both software and hardware source code in an open repository: https://github.com/vision-agh/gcnn-dvs-fpga .
@article{badap-agh:168430, title = {Embedded graph convolutional networks for real-time event data processing on SoC FPGAs}, author = {Jeziorek, Kamil and Wzorek, Piotr and Blachut, Krzysztof and Pinna, Andrea and Kryjak, Tomasz}, year = {2026}, journal = {Journal of Systems Architecture}, series = {Journal of Systems Architecture}, volume = {177}, pages = {103850}, doi = {10.1016/j.sysarc.2026.103850}, issn = {1383-7621}, collection = {Journal of Systems Architecture}, projects = {Preludium-Wzorek}, }

2025

ARC
Hardware-accelerated event-graph neural networks for low-latency time-series classification on SoC FPGA

Hiroshi Nakano, Krzysztof Blachut, Kamil Jeziorek, Piotr Wzorek, Manon Dampfhoffer, and 4 more authors

In Applied Reconfigurable Computing : architectures, tools, and applications : 21st international symposium, ARC 2025 : Seville, Spain, April 9–11, 2025 : proceedings, 2025

Abstract Collaboration DOI arXiv Bib
- Digital Systems and Integrated Circuits Division
  CEA-List Grenoble, France
- Faculty of Science and Technology, Department of System Design Engineering
  Keio University, Japan
All our collaborations
As the quantities of data recorded by embedded edge sensors grow, so too does the need for intelligent local processing. Such data often comes in the form of time-series signals, based on which real-time predictions can be made locally using an AI model. However, a hardware-software approach capable of making low-latency predictions with low power consumption is required. In this paper, we present a hardware implementation of an event-graph neural network for time-series classification. We leverage an artificial cochlea model to convert the input time-series signals into a sparse event-data format that allows the event-graph to drastically reduce the number of calculations relative to other AI methods. We implemented the design on a SoC FPGA and applied it to the real-time processing of the Spiking Heidelberg Digits (SHD) dataset to benchmark our approach against competitive solutions. Our method achieves a floating-point accuracy of 92.7% on the SHD dataset for the base model, which is only 2.4% and 2% less than the state-of-the-art models with over 10% and 67% fewer model parameters, respectively. It also outperforms FPGA-based spiking neural network implementations by 19.3% and 4.5%, achieving 92.3% accuracy for the quantised model while using fewer computational resources and reducing latency.
@inproceedings{badap-agh:160129, title = {Hardware-accelerated event-graph neural networks for low-latency time-series classification on SoC FPGA}, author = {Nakano, Hiroshi and Blachut, Krzysztof and Jeziorek, Kamil and Wzorek, Piotr and Dampfhoffer, Manon and Mesquida, Thomas and Nishi, Hiroaki and Kryjak, Tomasz and Dalgaty, Thomas}, year = {2025}, series = {Applied Reconfigurable Computing : architectures, tools, and applications : 21st international symposium, ARC~2025 : Seville, Spain, April 9–11,~2025 : proceedings}, pages = {51–68}, doi = {10.1007/978-3-031-87995-1_4}, collection = {Applied Reconfigurable Computing : architectures, tools, and applications : 21st international symposium, ARC~2025 : Seville, Spain, April 9–11,~2025 : proceedings}, }
CVPRW Preludium
Live demonstration: real-time event-data processing with Graph Convolutional Neural Networks and SoC FPGA

Piotr Wzorek, Krzysztof Blachut, Kamil Jeziorek, and Tomasz Kryjak

In CVPRW 2025 : IEEE/CVF Computer Vision and Pattern Recognition Workshops : 11–15 June 2025, Nashville, [USA] : proceedings, 2025

Abstract DOI Bib

With growing demand for robust low-power and lowlatency computer vision, event cameras are becoming increasingly common in mobile robotics and autonomous vehicles due to their high temporal resolution, ability to operate in adverse lightning conditions and reduction of redundant information. However, fully exploiting the benefits of these sensors requires algorithms capable of processing sparse data efficiently and optimised for a specialised target platform. To address this demand, we present a hardware-aware model of Graph Convolutional Neural Networks (GCNNs) implemented on an embedded heterogeneous SoC FPGA. Leveraging the temporal sparsity of event data, our approach integrates partially asynchronous processing and 3D MaxPool layers to achieve real-time, high-accuracy object classification on embedded platforms. A key strength of our architecture is its scalability – customisable hardware modules enable flexible configurations to balance resource utilisation and latency. In this realtime demonstration we will showcase the capabilities of our GCNN model, address its limitations, and discuss future development directions. We will use the system operating on a heterogeneous SoC FPGA to classify event data captured directly by the integrated camera or read from an SD card with simulated time intervals between events. Our work has been shared in a open-source repository: https://github.com/vision-agh/gcnn-dvs-fpga
@inproceedings{badap-agh:162625, title = {Live demonstration: real-time event-data processing with Graph Convolutional Neural Networks and SoC FPGA}, author = {Wzorek, Piotr and Blachut, Krzysztof and Jeziorek, Kamil and Kryjak, Tomasz}, year = {2025}, series = {CVPRW~2025 [Dokument elektroniczny] : IEEE/CVF Computer Vision and Pattern Recognition Workshops : 11–15 June~2025, Nashville, [USA] : proceedings}, pages = {5103–5104}, doi = {10.1109/CVPRW67362.2025.00505}, collection = {CVPRW~2025 [Dokument elektroniczny] : IEEE/CVF Computer Vision and Pattern Recognition Workshops : 11–15 June~2025, Nashville, [USA] : proceedings}, projects = {Preludium-Wzorek}, }
FPL Preludium
Preludium
Live demonstration: Continuous processing of event-data with Graph Convolutional Neural Networks implemented for SoC FPGA

Piotr Wzorek, Kamil Jeziorek, Marcin Kowalczyk, Krzysztof Blachut, Tomasz Kryjak, and 1 more author

In FPL 2025 : 35th International Conference on Field-Programmable Logic and Applications : 1–5 September 2025 Leiden, Netherlands : proceedings, 2025

Abstract DOI Bib

For perception systems in mobile robotics - particularly in demanding, highly dynamic environments - event cameras (DVS - Dynamic Vision Sensors) are being increasingly utilised as an alternative to conventional vision sensors. The real-time processing of the registered spatio-temporal sparse point cloud must satisfy stringent requirements in terms of latency, throughput, and energy efficiency. In this demonstration, we present our method for implementing Graph Convolutional Neural Networks on a heterogeneous SoC FPGA platform, aimed at meeting these constraints. We address the challenges associated with integrating event-based sensors with reconfigurable hardware, as well as the intricate relationship between latency, performance, and hardware resource utilisation.
@inproceedings{badap-agh:166922, title = {Live demonstration: Continuous processing of event-data with Graph Convolutional Neural Networks implemented for SoC FPGA}, author = {Wzorek, Piotr and Jeziorek, Kamil and Kowalczyk, Marcin and Blachut, Krzysztof and Kryjak, Tomasz and Gorgon, Marek}, year = {2025}, series = {FPL~2025 [Dokument elektroniczny] : 35th International Conference on Field-Programmable Logic and Applications : 1–5 September~2025 Leiden, Netherlands : proceedings}, pages = {359}, doi = {10.1109/FPL68686.2025.00065}, collection = {FPL~2025 [Dokument elektroniczny] : 35th International Conference on Field-Programmable Logic and Applications : 1–5 September~2025 Leiden, Netherlands : proceedings}, projects = {Preludium-Wzorek, Preludium-Kowalczyk}, }

2024

DASIP
Optimising graph representation for hardware implementation of graph convolutional networks for event-based vision

Kamil Jeziorek, Piotr Wzorek, Krzysztof Blachut, Andrea Pinna, and Tomasz Kryjak

In Design and Architectures for Signal and Image Processing : 17th international workshop, DASIP 2024 : Munich, Germany, January 17–19, 2024 : proceedings, 2024

Abstract Collaboration DOI arXiv Bib
- SYEL (Systèmes Électroniques), LIP6 laboratory
  Sorbonne Université, France
All our collaborations
Event-based vision is an emerging research field involving processing data generated by Dynamic Vision Sensors (neuromorphic cameras). One of the latest proposals in this area are Graph Convolutional Networks (GCNs), which allow to process events in its original sparse form while maintaining high detection and classification performance. In this paper, we present the hardware implementation of a graph generation process from an event camera data stream, taking into account both the advantages and limitations of FPGAs. We propose various ways to simplify the graph representation and use scaling and quantisation of values. We consider both undirected and directed graphs that enable the use of PointNet convolution. The results obtained show that by appropriately modifying the graph representation, it is possible to create a hardware module for graph generation. Moreover, the proposed modifications have no significant impact on object detection performance, only 0.08% mAP less for the base model and the N-Caltech data set.Finally, we describe the proposed hardware architecture of the graph generation module.
@inproceedings{badap-agh:154027, title = {Optimising graph representation for hardware implementation of graph convolutional networks for event-based vision}, author = {Jeziorek, Kamil and Wzorek, Piotr and Blachut, Krzysztof and Pinna, Andrea and Kryjak, Tomasz}, year = {2024}, series = {Design and Architectures for Signal and Image Processing : 17th international workshop, DASIP~2024 : Munich, Germany, January 17–19, 2024 : proceedings}, pages = {110–122}, doi = {10.1007/978-3-031-62874-0_9}, collection = {Design and Architectures for Signal and Image Processing : 17th international workshop, DASIP~2024 : Munich, Germany, January 17–19, 2024 : proceedings}, }

2023

SPA
High-definition event frame generation using SoC FPGA devices

Krzysztof Blachut and Tomasz Kryjak

In SPA 2023 : Signal Processing Algorithms, Architectures, Arrangements, and Applications : Poznan, 20th - 22nd September 2023, 2023

Abstract DOI arXiv Bib

In this paper we have addressed the implementation of the accumulation and projection of high-resolution event data stream (HD – 1280×720 pixels) onto the image plane in FPGA devices. The results confirm the feasibility of this approach, but there are a number of challenges, limitations and trade-offs to be considered. The required hardware resources of selected data representations, such as binary frame, event frame, exponentially decaying time surface and event frequency, were compared with those available on several popular platforms from AMD Xilinx. The resulting event frames can be used for typical vision algorithms, such as object classification and detection, using both classical and deep neural network methods.
@inproceedings{badap-agh:150127, title = {High-definition event frame generation using SoC FPGA devices}, author = {Blachut, Krzysztof and Kryjak, Tomasz}, year = {2023}, series = {SPA~2023 : Signal Processing Algorithms, Architectures, Arrangements, and Applications : Poznan, 20th - 22nd September 2023}, pages = {106–111}, doi = {10.23919/SPA59660.2023.10274447}, collection = {SPA~2023 : Signal Processing Algorithms, Architectures, Arrangements, and Applications : Poznan, 20th - 22nd September 2023}, }
PAR Preludium
Zliczanie szybkich obiektów z wykorzystaniem kamery zdarzeniowej

Kamil Bialik, Marcin Kowalczyk, Krzysztof Blachut, and Tomasz Kryjak

PAR Pomiary Automatyka Robotyka, 2023

Abstract DOI arXiv Bib

This paper proposes the use of an event camera as a component of a vision system that enables counting of fast-moving objects – in this case, falling corn grains. These cameras transmit, in an asynchronous manner, information about the change in brightness of individual pixels and are characterised by low latency, no motion blur, and correct operation in different lighting conditions, as well as very low power consumption. The proposed counting algorithm processes events in real time. The operation of the solution was demonstrated on a stand consisting of a chute with a vibrating feeder, which allowed the number of falling grains to be adjusted. The objective of the control system with a PID controller was to maintain a constant average number of falling objects. The proposed solution was subjected to a series of tests to determine the correctness of the developed method operation. On their basis, the validity of using an event camera to count small, fast-moving objects and the associated wide range of potential industrial applications can be confirmed.
@article{badap-agh:145827, title = {Zliczanie szybkich obiekt\'{o}w z wykorzystaniem kamery zdarzeniowej}, author = {Bialik, Kamil and Kowalczyk, Marcin and Blachut, Krzysztof and Kryjak, Tomasz}, year = {2023}, projects = {Preludium-Kowalczyk}, journal = {PAR Pomiary Automatyka Robotyka}, series = {PAR Pomiary Automatyka Robotyka}, volume = {27}, number = {1}, pages = {79}, doi = {10.14313/PAR_247/79}, issn = {1427-9126}, collection = {PAR Pomiary Automatyka Robotyka}, }

2022

JSPS
Automotive perception system evaluation with reference data from a UAV’s camera using ArUco markers and DCNN

Krzysztof Blachut, Michal Danilowicz, Hubert Szolc, Mateusz Wasala, Tomasz Kryjak, and 1 more author

Journal of Signal Processing Systems for Signal, Image, and Video Technology, 2022

Abstract DOI Bib

Testing and evaluation of an automotive perception system is a complicated task which requires special equipment and infrastructure. To compute key performance indicators and compare the results with real-world situation, some additional sensors and manual data labelling are often required. In this article, we propose a different approach, which is based on a UAV equipped with a 4K camera flying above a test track. Two computer vision methods are used to precisely determine the positions of the objects around the car – one based on ArUco markers and the other on a DCNN (we provide the algorithms used on GitHub). The detections are then correlated with the perception system readings. For the static and dynamic experiments, the differences between various systems are mostly below 0.5 m. The results of the experiments performed indicate that this approach could be an interesting alternative to existing evaluation solutions.
@article{badap-agh:141200, title = {Automotive perception system evaluation with reference data from a UAV's camera using ArUco markers and DCNN}, author = {Blachut, Krzysztof and Danilowicz, Michal and Szolc, Hubert and Wasala, Mateusz and Kryjak, Tomasz and Komorkiewicz, Mateusz}, year = {2022}, journal = {Journal of Signal Processing Systems for Signal, Image, and Video Technology}, series = {Journal of Signal Processing Systems for Signal, Image, and Video Technology}, volume = {94}, number = {7}, pages = {675}, doi = {10.1007/s11265-021-01734-3}, issn = {1939-8018}, collection = {Journal of Signal Processing Systems for Signal, Image, and Video Technology}, }
Electronics Sonata
Real-time CLAHE algorithm implementation in SoC FPGA device for 4K UHD video stream

Tomasz Kryjak, Krzysztof Blachut, Hubert Szolc, and Mateusz Wasala

Electronics, 2022

Abstract DOI Bib

One of the problems encountered in the field of computer vision and video data analysis is the extraction of information from low-contrast images. This problem can be addressed in several ways, including the use of histogram equalisation algorithms. In this work, a method designed for this purpose—the Contrast-Limited Adaptive Histogram Equalization (CLAHE) algorithm—is implemented in hardware. An FPGA platform is used for this purpose due to the ability to run parallel computations and very low power consumption. To enable the processing of a 4K resolution (UHD, 3840 × 2160 pixels) video stream at 60 fps (frames per second) by using the CLAHE method, it is necessary to use a vector data format and process multiple pixels simultaneously. The algorithm realised in this work can be a component of a larger vision system, such as in autonomous vehicles or drones, but it can also support the analysis of underwater, thermal, or medical images both by humans and in an automated system.
@article{badap-agh:141231, title = {Real-time CLAHE algorithm implementation in SoC FPGA device for 4K UHD video stream}, projects = {Sonata}, author = {Kryjak, Tomasz and Blachut, Krzysztof and Szolc, Hubert and Wasala, Mateusz}, year = {2022}, journal = {Electronics}, series = {Electronics}, volume = {11}, number = {14}, pages = {2248}, doi = {10.3390/electronics11142248}, issn = {2079-9292}, collection = {Electronics}, }
Sensors Sonata
Real-time efficient FPGA implementation of the multi-scale Lucas-Kanade and Horn-Schunck optical flow algorithms for a 4K video stream

Krzysztof Blachut and Tomasz Kryjak

Sensors, 2022

Abstract DOI Bib

The information about optical flow, i.e., the movement of pixels between two consecutive images from a video sequence, is used in many vision systems, both classical and those based on deep neural networks. In some robotic applications, e.g., in autonomous vehicles, it is necessary to calculate the flow in real time. This represents a challenging task, especially for high-resolution video streams. In this work, two gradient-based algorithms-Lucas-Kanade and Horn-Schunck-were implemented on a ZCU 104 platform with Xilinx Zynq UltraScale+ MPSoC FPGA. A vector data format was used to enable flow calculation for a 4K (Ultra HD, 3840 × 2160 pixels) video stream at 60 fps. In order to detect larger pixel displacements, a multi-scale approach was used in both algorithms. Depending on the scale, the calculations were performed for different data formats, allowing for more efficient processing by reducing resource utilisation. The presented solution allows real-time optical flow determination in multiple scales for a 4K resolution with estimated energy consumption below 6 W. The algorithms realised in this work can be a component of a larger vision system in advanced surveillance systems or autonomous vehicles.
@article{badap-agh:140919, title = {Real-time efficient FPGA implementation of the multi-scale Lucas-Kanade and Horn-Schunck optical flow algorithms for a~4K video stream}, projects = {Sonata}, author = {Blachut, Krzysztof and Kryjak, Tomasz}, year = {2022}, journal = {Sensors}, series = {Sensors}, volume = {22}, number = {13}, pages = {5017}, doi = {10.3390/s22135017}, issn = {1424-8220}, collection = {Sensors}, }

Book chapter Preludium

Systemy wizyjne w zastosowaniach przemyslowych

Marek Gorgon, Maciej Aleksandrowicz, Krzysztof Blachut, Andrzej Brodzicki, Zbigniew Bublinski, and 20 more authors

In Nauka – technika – technologia : seria wydawnicza AGH, 2022

Abstract DOI Bib

Streszczenie: Systemy wizyjne to dynamicznie rozwijająca się dziedzina nauki i techniki.W niniejszym artykule przedstawiono przegląd zagadnień, nad którymi pracuje zespół Laboratorium Systemów Wizyjnych.Obejmuje on systemy wizyjne dla pojazdów autonomicznych, aplikacje analizy obrazów medycznych, systemy wspomagania szkolenia pracowników, analizę obrazów termowizyjnych, implementacje i akceleracje algorytmów wizyjnych w układach SoC FPGA i GPU, przetwarzanie strumienia wizyjnego w rozdzielczości 4K, a także analizę sygnałów z wykorzystaniem głębokich sieci neuronowych i współpracę przy eksperymencie ALICE w CERN-ie.

@inbook{badap-agh:141409,
  title = {Systemy wizyjne w zastosowaniach przemyslowych},
  author = {Gorgon, Marek and Aleksandrowicz, Maciej and Blachut, Krzysztof and Brodzicki, Andrzej and Bublinski, Zbigniew and Cyba, Artur and Danilowicz, Michal and Glowacz, Adam and Jablonski, Miroslaw and Jaworek-Korjakowska, Joanna and Kostuch, Aleksander and Kowalczyk, Marcin and Kryjak, Tomasz and Kucharski, Dariusz and Lis, Konrad and Machura, Michal and Mikrut, Zbigniew and Pawlik, Piotr and Piekarski, Michal and Przewlocka-Rus, Dominika and Lis, Joanna and Szolc, Hubert and Wasala, Mateusz and Wojcicka, Anna Malgorzata and Wzorek, Piotr},
  year = {2022},
  projects = {Preludium-Kowalczyk},
  series = {Nauka – technika – technologia : seria wydawnicza AGH},
  volume = {T.~5},
  pages = {17–31},
  doi = {10.7494/978-83-67427-00-5_1},
  collection = {Nauka – technika – technologia : seria wydawnicza AGH},
}

2021

DASIP
Automotive perception system evaluation with reference data obtained by a UAV

Krzysztof Blachut, Michal Danilowicz, Hubert Szolc, Mateusz Wasala, Tomasz Kryjak, and 2 more authors

In DASIP 2021 : workshop on Design and Architectures for Signal and Image Processing - 14th edition : January 18–20 2021, Budapest, Hungary : proceedings, 2021

Abstract DOI Bib

Testing and evaluation of an automotive perception system is a complicated task which requires special equipment and infrastructure. To compute key performance indicators and compare the results with the real-world situation, some additional sensors and manual data labelling are often required. In this article, we propose a different approach, which is based on a UAV equipped with a 4K camera flying above the test track. Thanks to the synchronisation of the sensors between the tested vehicle and the UAV, it is possible to precisely determine the positions of the objects around the car and correlate them with the perception system readings. The performed experiments indicate that this approach could be an interesting alternative to the existing evaluation solutions.
@inproceedings{badap-agh:132409, title = {Automotive perception system evaluation with reference data obtained by a UAV}, author = {Blachut, Krzysztof and Danilowicz, Michal and Szolc, Hubert and Wasala, Mateusz and Kryjak, Tomasz and Pankiewicz, Nikodem and Komorkiewicz, Mateusz}, year = {2021}, series = {DASIP~2021 [Dokument elektroniczny] : workshop on Design and Architectures for Signal and Image Processing - 14th~edition : January 18–20 2021, Budapest, Hungary : proceedings}, pages = {10–18}, doi = {10.1145/3441110.3441151}, collection = {DASIP~2021 [Dokument elektroniczny] : workshop on Design and Architectures for Signal and Image Processing - 14th~edition : January 18–20 2021, Budapest, Hungary : proceedings}, }

2020

ICCVG
A vision based hardware-software real-time control system for the autonomous landing of an UAV

Krzysztof Blachut, Hubert Szolc, Mateusz Wasala, Tomasz Kryjak, and Marek Gorgon

In Computer Vision and Graphics : International Conference : ICCVG 2020 : Warsaw, Poland, September 14–16, 2020 : proceedings, 2020

Abstract DOI arXiv Bib

In this paper we present a vision based hardware-software control system enabling autonomous landing of a mul-tirotor unmanned aerial vehicle (UAV). It allows the detection of a marked landing pad in real-time for a 1280 x 720 @ 60 fps video stream. In addition, a LiDAR sensor is used to measure the altitude above ground. A heterogeneous Zynq SoC device is used as the computing platform. The solution was tested on a number of sequences and the landing pad was detected with 96% accuracy. This research shows that a reprogrammable heterogeneous computing system is a good solution for UAVs because it enables real-time data stream processing with relatively low energy consumption.
@inproceedings{badap-agh:130006, title = {A vision based hardware-software real-time control system for the autonomous landing of an UAV}, author = {Blachut, Krzysztof and Szolc, Hubert and Wasala, Mateusz and Kryjak, Tomasz and Gorgon, Marek}, year = {2020}, series = {Computer Vision and Graphics : International Conference : ICCVG~2020 : Warsaw, Poland, September 14–16, 2020 : proceedings}, pages = {13–24}, doi = {10.1007/978-3-030-59006-2_2}, collection = {Computer Vision and Graphics : International Conference : ICCVG~2020 : Warsaw, Poland, September 14–16, 2020 : proceedings}, }
ICCVG
Optimisation of a Siamese neural network for real-time energy efficient object tracking

Dominika Przewlocka-Rus, Mateusz Wasala, Hubert Szolc, Krzysztof Blachut, and Tomasz Kryjak

In Computer Vision and Graphics : International Conference : ICCVG 2020 : Warsaw, Poland, September 14–16, 2020 : proceedings, 2020

Abstract DOI arXiv Bib

In this paper the research on optimisation of visual object tracking using a Siamese neural network for embedded vision systems is presented. It was assumed that the solution shall operate in real-time, preferably for a high resolution video stream, with the lowest possible energy consumption. To meet these requirements, techniques such as the reduction of computational precision and pruning were considered. Brevitas, a tool dedicated for optimisation and quantisation of neural networks for FPGA implementation, was used. A number of training scenarios were tested with varying levels of optimisations – from integer uniform quantisation with 16 bits to ternary and binary networks. Next, the influence of these optimisations on the tracking performance was evaluated. It was possible to reduce the size of the convolutional filters up to 10 times in relation to the original network. The obtained results indicate that using quantisation can significantly reduce the memory and computational complexity of the proposed network while still enabling precise tracking, thus allow to use it in embedded vision systems. Moreover, quantisation of weights positively affects the network training by decreasing overfitting.
@inproceedings{badap-agh:130002, title = {Optimisation of a Siamese neural network for real-time energy efficient object tracking}, author = {Przewlocka-Rus, Dominika and Wasala, Mateusz and Szolc, Hubert and Blachut, Krzysztof and Kryjak, Tomasz}, year = {2020}, series = {Computer Vision and Graphics : International Conference : ICCVG~2020 : Warsaw, Poland, September 14–16, 2020 : proceedings}, pages = {151–163}, doi = {10.1007/978-3-030-59006-2_14}, collection = {Computer Vision and Graphics : International Conference : ICCVG~2020 : Warsaw, Poland, September 14–16, 2020 : proceedings}, }

2018

DASIP

Hardware implementation of multi-scale Lucas-Kanade optical flow computation algorithm – a demo

Krzysztof Blachut, Tomasz Kryjak, and Marek Gorgon

In dasip 2018 : conference on Design and Architectures for Signal and Image Processing : October 10–12 2018, Porto, Portugal, 2018

Bib

@inproceedings{badap-agh:118435,
  title = {Hardware implementation of multi-scale Lucas-Kanade optical flow computation algorithm – a~demo},
  author = {Blachut, Krzysztof and Kryjak, Tomasz and Gorgon, Marek},
  year = {2018},
  series = {dasip~2018 [Dokument elektroniczny] : conference on Design and Architectures for Signal and Image Processing : October 10–12 2018, Porto, Portugal},
  pages = {1–2},
  url = {https://web.fe.up.pt/~specs/events/dasip2018/files/paper_49.pdf},
  collection = {dasip~2018 [Dokument elektroniczny] : conference on Design and Architectures for Signal and Image Processing : October 10–12 2018, Porto, Portugal},
}

Experience 2

Research & Teaching Assistant

Software tester